This 14-bit analog-to-digital converter (ADC) uses pipelined architecture to achieve high performance at conversion rate up to 20 MSPS. Implemented internal automatic prestart calibration system allows to tune consequently offset and gain of each pipeline stage, that results in high static and dynamic parameters of the whole pipeline ADC. The fully differential architecture and dual correlated sampling effectively reduce sensitivity of the ADC to various kinds of external and internal noise sources.


  • 14-bit resolution
  • Sample rate: 20 MSPS
  • Differential nonlinearity: ±1 LSB
  • Integral nonlinearity: ±1.5 LSB
  • Effective number of bits at 3 MHz input: 12 bits 
  • Fully differential architecture
  • Differential input range: 2 Vp-p
  • Output clock for output data processing
  • Built-in calibration state machine for offset and gain calibration
  • Built-in serial peripheral interface (SPI) for parameters tuning including Speed-to-Power Сonsumption ratio trimming 
  • Built-in voltage reference requiring no external components
  • Optional usage of external references
  • Operating temperature: up to 125 °С