The TI-16DS is a high-speed, high-precision, 16-bit, delta-sigma ADC. The upsampling underlying the ADC operation allows to lower sensitivity to the clock signal phase jitter at the moment of high-frequency, high-amplitude signal sampling. The device consists of a delta-sigma modulator with MASH architecture and a digital filter including five cascade FIR-filters with decimation. Such approach allows to reduce the digital part of the ADC.


  • 16-bit resolution
  • Clock frequency: 32 MHz
  • Sample rate: 1 MSPS
  • Fully differential architecture
  • Integral nonlinearity: ±2 LSB
  • Differential nonlinearity: ±1 LSB
  • Effective number of bits: 14.5 bits
  • Input signal bandwidth: 500 kHz
  • Operating temperature range: -40°С..+110°С

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